CAVIGLIA , Daniele

Second-generation current conveyors (CCII) provide flexible building blocks for current-mode circuits. This paper discusses a novel design for the CMOS realization of a rail-to-rail fully differential CCII (FDCCII). The FDCCII is eventually obtained by suitably combining two instances of a four-terminal block, which in practice implements a...

Piezoelectric oxide semiconductor field effect transistor (i.e. POSFET) sensor is a class of piezoelectric semiconductor devices which has been proposed for tactile sensing. As these sensors have piezoelectric material on top of the NMOS transistor gate, their bias point behaviour became a matter of speculation for a designer. Therefore, while...

In this paper, we propose a design solution for implementing high-value resistance circuit, intended to bias the floating gate of PolyVinyliDene Fluorine (PVDF) based tactile sensors. The solution was proposed to design circuits based on Twin-tub and N-well processes. The formulations of mathematical equations were derived from EKV model. Our...

In this paper we present series of experimental results showing the vulnerability of tactile sensors called by name Piezoelectric Oxide Semiconductor Field Effect Transistors (POSFETs) toward light and bare touch. In fact these sensors have customized transistors on exposed silicon substrate/well. The result shows that by using a naked sensor...

In this work we propose a simple model for the operation of the short channel MOSFET in weak and strong inversion. This model shows a better agreement to experimental data than previous models and is well suited for use in circuit simulation programs.

Our paper focuses on the classification of surface defects in flat rolled strips in steel industry. Since this work aims at the classification of samples organized in a hierarchical way it seems natural to use a hierarchical approach. We choose a hierarchical neural architecture, based on the Multi Layer Perceptron, which, to some extent,...

Analog VLSI implementations of artificial neural networks are usually considered efficient for the small area and the low power consumption they require, but very poor in terms of programmability. In this paper, we present an approach to the design of analog VLSI neural information-processing systems with on-chip learning capabilities. We...

An ASIC analog chip which implements the basic computational primitives of a neural model with on-chip learning has been designed and fabricated using a 1.5 μm CMOS technology. The chip contains about 3K transistors arranged into a matrix of 8×4 synapses fully connected to 4 neurons. Using the chip as basic module, it is possible to obtain more...

This paper deals with PLA folding strategies: in particular, the accurate evaluation of the area used by folded PLA's is presented. Criteria are proposed to choose the best folding strategy among those considered, without performing all the possible foldings.

Gradient descent learning algorithms (namely Back Propagation and Weight Perturbation) can significantly increase their classification performances adopting a local and adaptive learning rate management approach. In this paper, we present the results of the comparison of the classification performance of the two algorithms in a tough...

This paper focuses on the design of hierarchical tree-structured neural networks and their application to complex classification problems. In particular, our approach examines the capabilities of Multi-Layer-Perceptrons (MLPs) and classification trees. We specifically propose a classification tree with two hierarchical levels where each node is...

The classification of handwritten digits through an analog feature extractor chip and neural classifier is discussed in this paper. The chip implements a feature extraction algorithm onto analog circuits; it extracts a set of 112 features from the input character (32 x 24 binary pixel matrix). The features, coded by current signals, are given...

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La complessita' dei circuiti integrati VLSI attualmente disponibili rende necessario il ricorso a tecniche di "progettazione assistita da calcolatore" (computer-aided design o CAD) in ogni fase del progetto e, in particolare, per il progetto fisico (layout). Nel metodo di progettazione a macrocelle, la complessita' del progetto viene gestita...