GUERRERO MARTOS , David

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This contribution describes the experience of updating a basic digital electronics course in a Computer Science grade as a consequence of the new grades introduced by the European Higher Education Area (EHEA) in a Spanish university. The group under study is special in because it is taught in English under a pilot scheme carried out by the...

Esta contribución presenta una experiencia sobre el proceso de adaptación de una asignatura de electrónica digital básica de primer curso de la titulación de Ingeniería Informática impartida por los autores en uno de sus grupos, con motivo de la implantación de los nuevos títulos de grado. El grupo tiene la particularidad de impartirse en...

En este trabajo se desarrolla un procesador académico para su uso en la asignatura Estructura de Computadores de primer curso de las nuevas titulaciones de Grado en Ingeniería Informática. En las prácticas de la asignatura se aplicarán los conceptos de sistemas digitales que ya poseen los alumnos al diseño e implementación de este...

An academic processor to be used in the "Computer Structure" subject has been developed in this work. During the lab sessions students will apply their knowledge about digital systems to design and implement this processor so they will interact with a real implementation of the system in several ways: modifying it to increase its functionality,...

Los profesores universitarios de áreas científicas y técnicas están cada vez más preocupados por desarrollar adecuadamente sus tareas docentes. Una muestra de este hecho se presenta en este trabajo en el que se describe la realización de un proyecto de formación de profesores noveles del área de Tecnología Electrónica. Los aspectos didácticos...

Se presenta una práctica de introducción al diseño de sistemas digitales sobre FPGAs. El objetivo es que se pueda realizar en los primeros cursos dedicados a sistemas digitales, para que la formación no sea fundamentalmente teórica sino eminentemente práctica aprovechando la enorme versatilidad que ofrecen las FPGAs. Se plantea como un tutorial...

This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it...

Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex...

In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we...

This paper presents the design of a complete RTU (Remote Terminal Unit) with a System-on-Chip solution based completely on both open hardware and software platforms, and developed in conjunction with two industrial companies. The target implementation of the embedded system is a Spartan family FPGA from Xilinx. The article presents the main...

In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although they are very basic machines they present problems common to every P system (competition, parallel execution of rules, membrane dissolution, etc.) that have to be solved in order to get real emulations for them. The...

Se presenta una práctica de introducción al diseño de sistemas digitales sobre FPGAs. El objetivo es que se pueda realizar en los primeros cursos dedicados a sistemas digitales, para que la formación no sea fundamentalmente teórica sino eminentemente práctica aprovechando la enorme versatilidad que ofrecen las FPGAs. Se plantea como un tutorial...

This paper presents the implementation of a configuration server for a SNTP synchronization platform which implements accurate synchronization solutions for Remote Terminal Units commonly used in industrial control processes. The configuration server provides settings to others platform devices using the BOOTP protocol and an interface that...

Many people may see the development of software and hardware like different disciplines. However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages. In this contribution, the approach proposed by the...

Este trabajo presenta el desarrollo de un sistema de radiocontrol para un coche teledirigido. Se trata de un circuito que, conectado al interfaz serie de un PC, permite controlar el coche desde una aplicación en lenguaje G. Así, el proceso de desarrollo se plantea como una práctica de laboratorio muy interesante y atractiva para los alumnos que...

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software...

In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal states the gate can reach. This computational model can be used in logiclevel tools and is valid for any dynamic behavioral...

Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper.

Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power...

NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be directly implemented in hardware. NanoFS is based on an original internal layout intended to achieve an optimal hardware implementation of the file system's file lookup and data fetch operations. File system...

Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces...

The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing analysis on each combinational block of the circuit. A key factor in timing analysis is the election of the delay model type. Pin-to-pin delay models are usually employed, but their application is limited in timing analysis...

It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves their timing and dynamic power characteristics. In this paper, the static power consumption of gates using this approach is addressed. When compared to conventional common body static CMOS, important static power...

In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase...