RUIZ DE CLAVIJO VÁZQUEZ , Paulino

El primer capítulo está dedicado a la simulación y verificación temporal de circuitos VLSI en general, así como a los fundamentos en los que se basan los simuladores lógicotemporales. En el segundo capítulo se realiza una revisión de los modelos de retraso, donde se recogen el efecto de degradación y el efecto inercial, proponiéndose un modelo...

En este trabajo, se presenta un sistema automático, basado en web, orientado a facilitar la organización de prácticas de laboratorio en asignaturas con elevado número de alumnos. Se caracteriza por permitir tanto su utilización como su administración mediante browser, cumplir con los necesarios requisitos de seguridad, y soportar acceso a los...

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Nowadays, honeypots are a key tool to attract attackers and study their activity. They help us in the tasks of evaluating attacker's behaviour, discovering new types of attacks, and collecting information and statistics associated with them. However, the gathered data cannot be directly interpreted, but must be analyzed to obtain useful...

The aim of this teaching innovation project is to look for deeply into knowledge about the theoretical base and construction of mathematical models that are the basis of electrical design, making use of setups, lectures, simulations and experimentations. The procedure is based upon the execution of essential experimental measurements at the...

In this contribution, the advantages of using a virtualization platform for IT laboratories is demonstrated. The platform used is based on free (open-source) software and present important advantages with respect to previous virtualization solutions since the new platform provides the students with greater control over their virtual machines....

En la Sociedad de la Información actual, Internet está presente en la mayoría de las actividades cotidianas que realizan las personas. Este hecho ofrece a las Universidades nuevas posibilidades de acercar sus titulaciones a personas que difícilmente podrían cursarlas de forma presencial debido a no poder compatibilizar los horarios de dichas...

In this article, the teaching of quality of service mechanisms in packet-switched networks is presented. To this end, a methodology based on virtualization technology is introduced. As a result, a truly practical approach is offered to students, in an accessible environment, and from a point of view suitable for the Bachelor's degree in...

Este trabajo abarca la aplicación de técnicas de calidad de servicio en redes de conmutación de paquetes. Para ello se presenta una metodología basada en técnicas de virtualización. Con ello se aporta al alumno un enfoque muy práctico y un entorno fácilmente accesible, todo ello desde un punto de vista adecuado a la titulación de Grado en...

This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it...

Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware...

This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for integrating Internet of Things (IoT) devices. IRIS can boot a Linux kernel image pre-stores in removable media and comprises a data verifier securing the authenticity, integrity, and confidentiality of the boot process. IRIS...

In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we...

This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by...

This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular...

Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the...

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model...

As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which is necessary to face in order to achieve a practical implementation of the model. In this way, this communication describes the characterization process associated to the previously...

Este trabajo presenta el desarrollo de un sistema de radiocontrol para un coche teledirigido. Se trata de un circuito que, conectado al interfaz serie de un PC, permite controlar el coche desde una aplicación en lenguaje G. Así, el proceso de desarrollo se plantea como una práctica de laboratorio muy interesante y atractiva para los alumnos que...

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software...

In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal states the gate can reach. This computational model can be used in logiclevel tools and is valid for any dynamic behavioral...

In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important...

Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper.

Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power...